`timescale 1ns / 1ns

module tb_fc_top;

    reg         clk;
    reg         rst_n_fc;
    reg         start;

    wire        done_o;

    // 第一层监视信号
    wire [31:0] fc1_output_data_monitor;
    wire        fc1_output_wren_monitor;

    // 第二层监视信号
    wire [47:0] fc2_output_data_monitor;
    wire        fc2_output_wren_monitor;

    // 第三层监视信号
    wire [63:0] fc3_output_data_monitor;
    wire        fc3_output_wren_monitor;

    fc_top u_fc_top(
        .clk(clk),
        .rst_n_fc(rst_n_fc),
        .start(start),
        .done_o(done_o),
        .fc1_output_data_monitor(fc1_output_data_monitor),
        .fc1_output_wren_monitor(fc1_output_wren_monitor),
        .fc2_output_data_monitor(fc2_output_data_monitor),
        .fc2_output_wren_monitor(fc2_output_wren_monitor),
        .fc3_output_data_monitor(fc3_output_data_monitor),
        .fc3_output_wren_monitor(fc3_output_wren_monitor)
    );

    integer fc1_file;
    integer fc2_file;
    integer fc3_file;

    initial begin
        fc1_file = $fopen("D:\\Verilog\\project_FullConnectionLayer\\fc1_out.txt", "w");
        fc2_file = $fopen("D:\\Verilog\\project_FullConnectionLayer\\fc2_out.txt", "w");
        fc3_file = $fopen("D:\\Verilog\\project_FullConnectionLayer\\fc3_out.txt", "w");
        if(fc1_file == 0 || fc2_file == 0 || fc3_file == 0) begin
            $display("[TB][ERROR] Failed to open output files.");
            $finish;
        end
    end

    always @(negedge clk) begin    // 在 clk 下降沿采集写使能
        if (fc1_output_wren_monitor) begin
            $fwrite(fc1_file, "%0d\n", $signed(fc1_output_data_monitor));
        end
        if (fc2_output_wren_monitor) begin
            $fwrite(fc2_file, "%0d\n", $signed(fc2_output_data_monitor));
        end
        if (fc3_output_wren_monitor) begin
            $fwrite(fc3_file, "%0d\n", $signed(fc3_output_data_monitor));
        end
    end

    initial begin
        forever #5 clk = ~clk;
    end

    initial begin
        clk = 0;
        rst_n_fc = 0;
        start = 0;
        #20 rst_n_fc = 1;
        #10 start = 1;
    end

    reg [7:0] count;
    always @(posedge clk or negedge rst_n_fc) begin
        if(!rst_n_fc) count <= 0;
        else count <= count + done_o;
    end

    always @(posedge clk) begin
        if(count == 41) begin
            $display("[TB][INFO] fc_top done asserted @%0t", $time);
			$fclose(fc1_file);
			$fclose(fc2_file);
			$fclose(fc3_file);
            #10 $finish;
        end
    end

endmodule
